1. Technical Field
The present invention relates to the fabrication of semiconductor microchip structures, and more particularly to methods for forming contact holes in microchips for establishing electrical contact between integrated circuit wiring.
2. Background Art
Photolithographic techniques permit certain portions of semiconductor materials on a circuit chip to be selectively removed or modified such that a layer of electrically connected devices such as transistors and capacitors can be formed.
A single layer of a circuit chip may be electrically connected in a number of ways. One way is to use the selective deposition and removal of a metal to create lines of metal on the surface of a chip to connect circuit components. In such processes, a thin metallic film such as copper, aluminum or tungsten is deposited over the surface of the chip. A layer of photoresist is then applied over the film and exposed to light of an appropriate wavelength using a mask that exposes a pattern of relatively narrow lines on the photoresist. The photoresist is then developed and etched, leaving metal in the pattern exposed on the resist. This pattern of metal forms the electrical connections for the single layer of the chip.
Another method of electrically connecting one layer of a chip is known as the damascene process. In the damascene process a dielectric such as silicon dioxide is deposited offer the surface of a chip. A layer of photoresist is applied to the silicon dioxide layer. The resist is then exposed to establish the desired pattern of interconnections. The photoresist is then developed and etched to produce trenches in the silicon dioxide pattern to form the interconnections for the layer. A metal layer such as aluminum, copper or tungsten is deposited over the surface of the chip to fill the trenches. The metal is then planarized so that it is removed from the surface of the chip except where it filled in the trenches. The metal filled trenches form a pattern of interconnections. Horizontal metal connections are referred to as wires and a typical chip includes one layer of devices and multiple layers of wires connected to the devices.
Although a microchip may consist of a single layer of wiring, normally several layers of wiring are needed for sufficient chip function. The layers of a microchip are typically separated by silicon dioxide or other dielectric to prevent one layer of a chip from interfering with the operation of another layer. The component devices on the layers of the chip however, must be electrically connected at appropriate locations through the silicon dioxide in order to interact. Thus, the silicon dioxide separating the wiring layers must be penetrated at the appropriate locations for the components on different layers to be electrically connected.
One way to electrically connect the layers of a chip is referred to as the dual damascene method. The dual damascene method is similar to the damascene process. The first step in the dual damascene process is to create trenches in the silicon dioxide for wires as previously described. The second step is to create openings through the silicon dioxide to a lower chip layer. The openings are made using a process of applying a resist, masking, exposing, developing and etching, as described hereinabove. The openings through a layer of silicon dioxide are referred to as vias. Typically, a via must be created through the silicon dioxide to extend between trenches on adjacent layers.
The dual damascene method of electrically connecting layers of a microchip requires careful alignment of vias and trenches. The tolerances that must be allowed to assure proper alignment of vias and trenches limits the density that may be obtained on a microchip. The conventional method of fabricating vias and trenches is to first create the trenches and then create the vias, as separate steps in the process.
An improvement in creating vias and trenches is disclosed in U.S. patent application, Ser. No. (Docket BU9-97-182), filed Nov. 30, 1998 by Furukawa et al. entitled A METHOD FOR FORMING SELF-ALIGNED FEATURES. The improvement employs a method for creating self-aligned vias and trenches by using two layers of resist, one of which masks the underlying layer such that a via may be formed only where a trench has been formed. This method employs two different photoresists layered one on top of the other. The lower photoresist layer (for the vias) is only exposed where the upper pliotoresist layer (for the trenches is also exposed. The result is that vias may only be created where a trench is to be created, and the vias and trenches are therefore self-aligned, and the wires formed in the trenches and connecting studs formed in the vias will also be self-aligned.
It is known that the lithographic scaling of contact holes in integrated circuits is more difficult than the lithographic sealing of line/space patterns because the optical enhancement techniques of off-axis illumination and alternating phase edge reticles cannot be applied to contact hole features.
These enhancement techniques provide good results when they are used with tightly nested features, or for isolated dark patterns. However, the techniques provide very little enhancement of isolated bright images such as with contact holes.
Previously, contacts have been scaled by printing a contact hole as the intersection of two perpendicular phase-edge line/space patterns on photoresist film prior to development, with two different reticles.